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Chapter 1: SP623 Board Features and Operation
Table 1-9:
User DIP Switches
FPGA Pin
J26
J25
K26
K24
G26
G25
H26
H24
Net Name
SW1
SW2
SW3
SW4
SW5
SW6
SW7
SW8
Reference
Designator
SW7
User Push Buttons (Active High)
[ Figure 1-2 , callout 15 ]
SW5 and SW6 are active-High user push buttons that are connected to user I/O pins on the
FPGA, as identified in Table 1-10 . These switches can be used for any purpose determined
by the user.
Table 1-10:
User Push Buttons
FPGA Pin
M26
M24
Net Name
PB_SW1
PB_SW2
Reference
Designator
SW6
SW4
User Test I/O
[ Figure 1-2 , callout 16 ]
A standard 2 x 6, 100-mil pitch header (J44) brings out 6 FPGA I/O for test purposes.
Table 1-11 lists these pins.
Table 1-11:
User Test I/O
20
FPGA Pin
U1
U2
V1
V3
AA13
AB13
Net Name
IO_L40N_M3DQ7_3_U1
IO_L40P_M3DQ6_3_U2
IO_L39N_M3LDQSN_3_V1
IO_L39P_M3LDQS_3_V3
IO_L36N_2_AA13
IO_L36P_2_AB13
www.xilinx.com
J44 Pin
2
4
6
8
10
12
SP623 Board User Guide
UG751 (v1.1) September 15, 2010
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